1. Field of the Invention
This invention relates to data processing systems. More particular, this invention relates to data processing systems incorporating a processing pipeline including a fetch stage which attempts to fetch data from a cache memory where that data may or may not be present within the cache memory.
2. Description of the Prior Art
It is known to provide data processing systems with processing pipelines such that the overall processing of a program instruction or a thread of program instructions may be divided between the pipelined stages and so the execution of many program instructions or threads can be overlapped in a manner substantially increasing instruction processing throughput.
Within such processing systems it is also known to provide cache memories which store a copy of data stored within a main memory. The copy of the data stored in the cache memory is more rapidly accessible than the data stored in the main memory. If a program instruction or thread attempts to access data which is not present within the cache memory, then the progress of that program instruction or thread is delayed until the data concerned becomes available. In some systems, a cache miss may cause the whole instruction pipeline to stall with further processing not being possible until the data which was the subject of the cache miss is returned from the main memory many processing cycles later. In order to overcome this processing bottleneck, it is known to provide systems such as out-of-order processors which seek to reorder program instruction execution such that stalled program instructions need not prevent the processing of subsequent program instructions in the program order which do not depend upon those stalled instructions.
Another known approach to the problem of cache misses is to issue a query to the cache for the data required by a program instructional thread significantly in advance of that data actually being required by the program instructional thread. If a cache miss occurs, then this advance querying of the cache permits a sufficient time that the data missing from the cache memory may be fetched to the cache memory before it is actually required. However, a problem with this approach is that given the high latency which can be associated with a requirement to fetch data from a main memory when a miss has occurred in the cache memory, it becomes necessary to query the cache so far in advance of the data being required that the needed buffering requirements for program instructions of threads in progress along the pipeline between the stage at which the query is performed and the stage at which the data is required become excessively large. Excessive buffering requirements are disadvantageous in terms of circuit size, power consumption, cost and other factors.